
.globl _start

_start:
     // msr SCR_EL3, xzr  // Ensure NS bit is initially clear, so secure copy of ICC_SRE_EL1 can be configured
    mov x0, #0x530
    msr scr_el3, x0

    //
    // neither EL3 nor EL2 trap floating point or accesses to CPACR
    //
    // msr CPTR_EL3, xzr
    ldr x1, =0x00000100
    msr CPTR_EL3, x1
    // msr CPTR_EL2, xzr
    ldr x1, =0x000033ff
    msr CPTR_EL2, x1

    mov x0, #1 << 8
    msr CPTR_EL3, x0            /* sve trap */

    mov x0, #3 << 20
    mov x1, #3 << 16            /* sve Enable */
    orr x0, x0, x1              
    // 0x00330000
    msr cpacr_el1, x0           /* Enable FP/SIMD */
    msr mdscr_el1, xzr

    // config for el change
    ldr x1, =0x80000000
    msr HCR_EL2, x1

    // #include "sys_reg.S"

    // ldr x1, =0x5c00000
    // msr fpcr, x1
    // #include "ini_sysreg.S"

//     ldr x1, =0x600003c0
//     msr spsr_el3,x1
//     adr x1, _el1_entry
//     msr ELR_EL3, x1
    

//     eret
// _el1_entry:
    // #include "sub_test/old_isa.S"
    // #include "sub_test/ld1w_test.S"
    // #include "sub_test/orn_isa.S"
    // #include "sub_test/incp_isa.S"
    // #include "sub_test/ptrue.S"
    // #include "sub_test/sqdecb.S"
    // #include "sub_test/udot.S"
    // #include "sub_test/pnext.S"
    // #include "sub_test/sqdecp_ldr.S"
    // #include "sub_test/ld1d.S"
    // #include "sub_test/uzp2.S"
    // #include "sub_test/uzp1.S"
    // #include "sub_test/cmpls.S"
    // #include "sub_test/sqsub.S"
    // #include "sub_test/cmplo.S"
    // #include "sub_test/sel_rev.S"
    // #include "sub_test/addvl_mov.S"

    #include "sub_test/tmp.S"

    // ldr x1, =0x600003cc
    // msr spsr_el1,x1
    // adr x1, _el3_end
    // msr ELR_EL1, x1

    // eret

// _el3_end:
    // exit run
    // mrs x1, fpcr
    // mrs x1, fpsr
    mov x1, #0x4
    ldr x2, =0x1300000
    strb w1, [x2]
    dsb sy

_i_wfe:
    wfe
    b _i_wfe

    ldr x1, =0x2230000
    br x1
